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www.irf.com ? 2011 international rectifie r september 29, 2011 irs2548d smps/led driver pfc + half-bridge control ic features ? pfc, system control and half-bridge driver in one ic ? critical-conduction mode boost-type pfc ? programmable pfc over-current protection ? half bridge driver ? half bridge over current protection ? variable frequency oscillator ? fixed internal 1.6us ho and lo deadtime ? internal bootstrap mosfet ? internal 15.6v zener clamp diode on vcc ? micropower startup (250 a) ? latch immunity and esd protection typical applications ? isolated led drivers ? power supplies product summary topology half bridge v offset 600v v out vcc i o+ & i o- (typical) 500ma/500ma t on & t off (typical) 120ns/50ns deadtime (typical) 1.6us package 14-lead soic typical connection diagram rvbus1 rlo + rvbus2 c1 l n rv1 f1 cvs dc p2 dcp1 ccomp coc ro c mpfc cv bu s2 cv bus1 rpfc rzx cvbus rvbus rfmin rvcc ccs r cs rf1 rlm1 rlm2 rho mhs ml s cbs cvcc1 cvcc + + br 1 c2 l1 cy gnd dpfc lp fc rfmax cres dout1 dout2 cout rpu r cl cvs reg +5v led+ led- rd1 rd2 rd3 rv1 rv2 cf1 cf2 2 enn 1 2 3 vbus 4 5 7 fm in 6 7 8 13 12 11 10 9 14 oc comp zx pfc ho vs vb vcc com lo cs irs2548d roc do1 do2 u1 u2a u2b u3 rf2 rmax cmax
irs2548d www.irf.com ? 2011 international rectifie r 2 table of contents page description 3 qualification information 4 absolute maximum ratings 5 recommended operating conditions 6 electrical characteristics 6 functional block diagram 9 state diagram 10 input/output pin equivalent circuit diagram 11 lead definitions 12 lead assignments 12 application information and additional details 13 package details 19 tape and reel details 20 part marking information 21 ordering information 22
irs2548d www.irf.com ? 2011 international rectifie r 3 description the irs2548d is a fully integrated, fully protected 600v led or switched mode power supply control ic with integrated pfc control for a boost pre-regulat or. the irs2548d is based on the popular irs2168d electronic ballast control ic re-designed for use in le d driver or half-bridge pow er supply applications. the pfc circuitry operates in critical conduction mode and provides high pf, low thd and dc bus regulation. the irs2548d features include programmable mini mum run frequency and adjustable oscillator frequency that can be driven by an opto isolat or or other feedback circuit in a feedback loop for frequency modulation in resonant systems. the irs2548d also includes pfc over-voltage and ove r-current protection, half bridge over current protection and a logic level enable input that can be used for pwm dimming in led drivers or general burst mode operation.
irs2548d www.irf.com ? 2011 international rectifie r 4 qualification information ? industrial ?? qualification level comments: this family of ic s has passed jedec?s industrial qualification. ir?s consumer qualification level is granted by extension of the higher industrial level. moisture sensitivity level msl2 ??? 260c (per ipc/jedec j-std-020) machine model class a (per jedec standard jesd22-a115) esd human body model class 1c (per eia/jedec standard eia/jesd22-a114) ic latch-up test class i, level a (per jesd78) rohs compliant yes ? qualification standards can be found at international rectifier?s web site http://www.irf.com/ ?? higher qualification ratings may be available should t he user have such requirements. please contact your international rectifier sales r epresentative for further information. ??? higher msl ratings may be available for the specific package types listed here. please contact your international rectifier sales repr esentative for further information.
irs2548d www.irf.com ? 2011 international rectifie r 5 absolute maximum ratings absolute maximum ratings indicate sustained limit s beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to co m, all currents are defined positive into any lead. the thermal resistance and power dissipation ra tings are measured under board mounted and still air conditions. symbol definition min. max. units v b vb pin high-side floating supply voltage -0.3 625 v s vs pin high-side floating supply offset voltage v b ? 25 v b + 0.3 v ho ho pin high-side floating output voltage v s - 0.3 v b + 0.3 v lo lo pin low-side output voltage v pfc pfc gate driver output voltage -0.3 v cc + 0.3 v io max maximum allowable output current (ho, lo, pfc) due to external power transistor miller effect -500 500 ma icc vcc current ? 0 25 ma v vbus vbus pin voltage v comp comp pin voltage voc oc pin voltage v enn sd/eol pin voltage v cs cs pin voltage -0.3 v cc + 0.3 v vzx zx pin voltage -0.3 vzx clamp + 0.3 v i fmin fmin pin current i comp comp pin current i zx zx pin current i oc oc pin current i enn enn pin current i cs cs pin current -5 5 ma dv/dt allowable vs pin offset voltage slew rate -50 50 v/ns p d package power dissipation @ ta +25oc pd = (t jmax -t a )/r ja --- 1.0 w r ja thermal resistance, junction to ambient --- 120 oc/w t j junction temperature -55 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) --- 300 oc ? this ic contains a zener clamp structure between the chip v cc and com, with a nominal breakdown voltage of 15.6 v. please note that this supply pin should not be driven by a low impedance dc power source greater than v clamp specified in the electrical characteristics section.
irs2548d www.irf.com ? 2011 international rectifie r 6 recommended operating conditions for proper operation the device should be used within recommended conditions. symbol definition min. max. units v b -v s high side floating supply voltage v bsuv+ v clamp v v s steady state high-side floating supply offset voltage -1 600 v cc supply voltage v ccuv+ v clamp i cc v cc supply current ?? 10 i enn enn pin current i cs cs pin current i oc oc pin current i zx zx pin current -1 1 ma r fmin fmin pin programming resistor 10 300 kohm v b -v s high side floating supply voltage -25 125 oc ?? sufficient current should be supplied to v cc to keep the internal 15.6 v zener regulating at v clamp . electrical characteristics v cc = v bs = v bias =14v +/- 0.25v, c lo = c ho = c pfc = 1000pf, rfmin = 42.2kohm, venn = v comp = v cs = v oc = vbus = vzx = 0v, t a =25c unless otherwise specified. symbol definition min typ max units test conditions supply characteristics v ccuv + v cc supply undervoltage positive going threshold 11.5 12.5 13.5 v v cc rising from 0v v ccuv - v cc supply undervoltage negative going threshold 9.5 10.5 11.5 v cc falling from 14v v uvhys v cc supply undervoltage lockout hysteresis 1.5 2.0 3.0 i qccuv uvlo mode v cc quiescent current --- 250 --- a v cc = 8v iqccflt vcc quiescent current in fault mode --- 400 --- mode=fault i ccrun run mode v cc supply current --- 5.5 --- ma mode = run vbus=4v enn=1nf pfc off time = 5us v clamp v cc zener clamp voltage 14.6 15.6 16.6 v i cc = 10ma
irs2548d www.irf.com ? 2011 international rectifie r 7 electrical characteristics (cont?d) v cc = v bs = v bias =14v +/- 0.25v, c lo = c ho = c pfc = 1000pf, rfmin = 42.2kohm, venn = v comp = v cs = v oc = vbus = vzx = 0v, t a =25c unless otherwise specified. symbol definition min typ max units test conditions floating supply characteristics i bs v bs supply current --- 0.9 1.3 ma mode=run v bsuv+ v bs supply undervoltage positive going threshold 8.0 9.0 10.0 v bs rising from 0v v bsuv- v bs supply undervoltage negative going threshold 7.0 8.0 9.0 v v bs falling from 14v i lkvs v s offset supply leakage current --- --- 50 ua v b = v s = 600v pfc error amplifier characteristics i comp source comp pin ota error amplifier output current sourcing --- 30 --- ua mode = run v vbus = 3.5v vcomp=4.0v i comp sink comp pin ota error amplifier output current sinking --- -30 --- mode = run v vbus = 4.5v vcomp=4.0v v compoh ota error amplifier output voltage swing (high state) --- 12.5 --- v vbus=3.5v icomp=icomp_ source - 5ua v compol ota error amplifier output voltage swing (low state) --- 0.4 --- vbus=5.0v icomp=icomp_ sink + 5ua vcompflt ota error amplifier output voltage in fault mode --- 0 --- vbus=4.0v pfc control characteristics v vbus reg vbus internal reference voltage 3.93 4.03 4.13 v vbusov vbus over-voltage comparator threshold 4.1 4.3 4.5 v v vbusov hys vbus over-voltage comparator hysteresis 50 150 300 mv v comp = 4.0v v zx zx pin threshold voltage 1.8 2.0 2.2 v v zxhys zx pin comparator hysteresis --- 300 --- mv v zxclamp zx pin clamp voltage (high state) --- 6.7 --- v i zx = 1ma t blank oc pin current-sensing blank time --- 300 --- ns vbus=4.0v vcomp=4.0v t wd pfc watch-dog pulse interval --- 400 --- us zx = 0, v comp = 4.0v pfc protection circuitry characteristics v octh+ oc pin over-current sense threshold 1.1 1.2 1.3 vbus=vcomp =4.0v
irs2548d www.irf.com ? 2011 international rectifie r 8 electrical characteristics (cont?d) v cc = v bs = v bias =14v +/- 0.25v, c lo = c ho = c pfc = 1000pf, rfmin = 42.2kohm, venn = v comp = v cs = v oc = vbus = vzx = 0v, t a =25c unless otherwise specified. symbol definition min typ max units test conditions system control oscillator characteristics f oscrun half-bridge oscillator run frequency 42.5 44.5 46.5 khz mode = run d oscillator duty cycle --- 50 --- td lo lo output deadtime --- 1.6 --- us td ho ho output deadtime --- 1.6 --- v fmin fmin pin voltage 1.9 2.0 2.1 v vcc = 14.0v v fminflt fmin pin fault or uvlo mode voltage --- 0 --- mode = fault or uvlo system control protection circuitry characteristics v csth+ cs pin over-current s ense threshold 1.15 1.25 1.35 v n events cs pin fault counter no. of events 65 mode = run v ennth+ sd pin rising non-latched shutdown threshold voltage --- 2.0 --- v ennth- sd pin falling reset threshold voltage --- 1.5 --- v v ennbias eol pin internal bias voltage --- 0v --- v v fminflt fmin pin fault mode voltage --- 0 --- v mode = fault gate driver output characteristics (ho, lo and pfc pins) v ol low-level output voltage --- 0 100 i o = 0 v oh high-level output voltage --- 0 100 mv v bias - v o , i o = 0 t r turn-on rise time --- 120 --- t f turn-off fall time --- 50 --- nsec i0+ source current --- 180 --- i0- sink current --- 260 --- ma bootstrap fet characteristics vb_on vb when the bootstrap fet is on --- 13.7 --- v ib_cap vb source current when fet is on 35 55 --- ma cbs=0.1uf ib_10v vb source current when fet is on 8 12 --- vb=10v
irs2548d www.irf.com ? 2011 international rectifie r 9 functional block diagram pfc comp zx 5.5v 2v q s r2 q r1 q s rq vcc oc vcc fmin com vbus vb ho vs lo cs high- side driver low- side driver 1.25v 8 11 6 2 1 12 14 13 9 5 3 4 vcc uvlo 300us watchdog timer 10 ovp 4.3v 60 event fault counter 4.0v ota1 driver and deadtime logic 15.6v 1.25v bootstrap control vcc 200ns blank time r enn 7 0v 2v 1.5v half bridge control pfc control in out 2v 2v i fmin r rfmin i fmin = +/-10ua fault logic oscillator vcc q s r q values in block diagram are typical values
irs2548d www.irf.com ? 2011 international rectifie r 10 state diagram all values are typical. please refer to application diagram on page 1.
irs2548d www.irf.com ? 2011 international rectifie r 11 input/output pin equivalent circuit diagrams vcc com vbus, fmin, comp, zx, pfc, oc, enn, cs esd diode esd diode 15v
irs2548d www.irf.com ? 2011 international rectifie r 12 lead definitions symbol description vbus dc bus sensing input fmin oscillator minimum frequency setting comp pfc error amplifier compensation zx pfc zero-crossing detection pfc pfc gate driver output oc pfc current sensing input enn enable / pwm dimming input cs half-bridge curr ent sensing input lo low-side gate driver output com ic power & signal ground vcc logic & low-side gate driver supply vb high-side gate driver floating supply vs high voltage floating return ho high-side gate driver output lead assignments 13 12 11 10 9 com vcc vb vs ho 1 2 3 vbus 4 5 7 comp fmin 6 7 pfc zx 8 enn lo cs 14 oc
irs2548d www.irf.com ? 2011 international rectifie r 13 application information and additional details i. led driver section functional description under-voltage lock-out mode (uvlo) the under-voltage lock-out mode (uvlo) is defined as the state the ic is in when vcc is below the turn-on threshold of the ic. the irs2548d undervoltage lock-out is designed to maintain an ultra low supply current and to guarantee the ic is fully functional before the high and low-side output drivers and pfc are activated. figure 1 shows a possible vcc supply voltage scheme using the micro-power start-up current of the irs2548d together with a snubber charge pump from the half- bridge output (r vcc , c vcc1 , c vcc2 , c snub , d cp1 and d cp2 ). irs2548d lo com vb vs ho v bus (+) v bus (-) vcc c bs 14 mhs c vcc2 r vcc d cp1 d cp2 to load r cs c snub mls 13 12 11 10 9 v rect (+) c vcc1 cs 8 r 3 c cs ic com load return r 1 r 2 r lo r ho bsfet control bsfet figure 1: start-up and supply circuitry. the vcc capacitors (c vcc1 and c vcc2 ) are charged by the current through supply resistor (r vcc ) minus the start-up current drawn by the ic. this resistor is chosen to set the desired ac line input voltage turn- on threshold for the system. when the voltage at vcc exceeds the ic star t-up threshold (vccuv+) and the enn pin is below 1.5 volts, the ic turns on and lo begins to oscillate. the capacitors at vcc begin to discharge due to the increase in ic operating current (figure 2). the high-side supply voltage, vb-vs, begins to increase as capacitor c bs is charged through the internal bootstrap mosfet during the lo on-time of each lo switching cycle. when the vb-vs voltage exceeds the high-side start-up threshold (vbsuv+), ho then begins to oscillate. this may take several cycles of lo to charge vb-vs above vbsuv+ due to rdson of the internal bootstrap mosfet. discharge time internal vcc zener clamp voltage vhyst v uvlo+ v uvlo- charge pump output t v c1 r vcc & c vcc1,2 time constant c vcc discharge figure 2: vcc supply voltage. when lo and ho are both oscillating, the external mosfets (mhs and mls) are turned on and off with a 50% duty cycle and a non- overlapping deadtime of 1.6us. the half-bridge output (pin vs) begins to switch between the dc bus voltage and com. during the deadtime between the turn-off of lo and the turn- on of ho, the half-bridge output voltage transitions from com to the dc bus voltage at a dv/dt rate determined by the snubber capacitor (c snub ). as the snubber capacitor charges, current will flow through the charge pump diode (d cp2 ) to vcc. after several switching cycles of the half-bridge output, the charge pump and the internal 15.6v zener clamp of the ic take over as the supply voltage. capacitor c vcc2 supplies the ic current during the vcc discharge time and should be large enough such that vcc does not decrease below uvlo- before the charge pump takes over. this scheme can be used in non-dimming applications, however w here pwm dimming is used the charge pump may not supply enough current to vcc at low dimming levels and in this case an auxiliary power supply is required. capacitor c vcc1 is required for noise filtering and must be placed as close as possible and directly between vcc and com, and should not be lower than 0.1uf. resistors r 1 and r 2 are recommended for limiting high currents that can flow to vcc from the charge pump. the internal bootstrap mosfet and supply capacitor (c bs ) provide the floating supply voltage for the high side driver circuitry. during uvlo mode the high and low-side driver outputs ho and lo are both low and the internal oscillator is disabled.
irs2548d www.irf.com ? 2011 international rectifie r 14 run mode (run) after the vcc supply comes up and the ic starts, the ic enters run mode. the operating frequency is set to the minimum limit, which is programmed by the external resistor (rfmin ) at the fmin pin. if the irs2548d is used in a series resonant configuration the frequency can be increased to regulate the system output voltage. this can be implemented by sinking additional current from the fmin pin with an additional resistor, opto isolator or other arrangement. it should be noted that the fmin pin input is very sensitive to noise and that traces connected to this pin should be very short and should be kept away from high voltage switching nodes; ho, vb and vs. an additional rc filter can also be added to the fmin pin if necessary as shown in the application schematic on page 1. should hard-switching occur at the half-bridge at any time or excessive current be drawn due to a fault condition, the voltage across the current sensing resistor (rcs) will exceed the internal threshold of 1.2 volts (vcsth+) and the fault counter will begin counting (see figure 3). cs fault mode the current sense function will force the ic to enter fault mode only after the voltage at the cs pin has been greater than 1.2v (vcsth+) for 65 (nevents) consecutive cycles of lo. the voltage at the cs pin is and-ed with lo (see figure 3) so it will work with pulses that occur during the lo on- time or dc. if the over-current faults are not consecutive, then the internal fault counter will count back down each cycle when there is no fault. should an over-current fault occur only for a few cycles and then not occur again, the counter will eventually reset to zero. lo cs 65 cycles run mode fault mode 1.25v figure 3: fault counter timing diagram. dim mode (enn input) pwm dimming can be implemented via the enn pin. if the voltage input to the enn pin exceeds 2v during run mode, the ic enters dim mode, lo, ho and pfc gate drivers go to the low state. this is similar to fault mode except that the comp pin is not internally pulled to com and so the comp capacitor retains it's voltage. this allows the pfc to start up rapidly with the on time close to where it was before the enn signal shut off the ic outputs. when enn goes below 1.5v and therefore the bus voltage can be maintained while the pfc gate drive being held low during the periods where the led load is not being driven. this minimizes ripple generated on the dc bus during pwm dimming.
irs2548d www.irf.com ? 2011 international rectifie r 15 ii. pfc section functional description in most led drivers rated at more than a few watts high power factor high power factor (pc) is a requirement. the driver needs to appear as a resistive load to the ac input line voltage. the degree to which the circuit matches a purely resistive load is measured by the phase shift between the input voltage and input current harmonic distortion of the input current waveform. the cosine of the phase angle between the input voltage and input current is defined as the displacement power facto r and the amount of harmonic distortion determines the distortion power factor and total harmonic distortion (thd). the overall power factor is the ratio between real and apparent power and includes both displacement and distortion. a power factor of 1.0 corresponds to zero phase shift and a thd of 0% representing a pure sinusoidal current waveform. in order to provide a high pf and a low thd the irs2548d includes an active power factor correction (pfc) circuit. the control method implemented in the irs2548d is designed for a pfc boost converter (figure 4) running in critical-conduction mode , the boundary between continuous and discontinuous mode. during the off period of eac h switching cycle of the pfc mosfet the circuit waits until the inductor current falls to zero before turning the pfc mosfet on again. the pfc mosfet is turned on and off at a much higher frequency (>10khz) than the line input frequency (50 to 60hz). cbus + (+) (-) mpfc lpfc dpfc dc bus figure 4: boost converter circuit. when the switch mpfc is turned on the inductor lpfc is connected between the rectified line input (+) and (-) causing the current in lpfc to rise linearly. when mpfc is turned off lpfc is connected between the rect ified line input (+) and the dc bus capacitor cbus through diode dpfc and the stored energy in lpfc supplies a current into cbus. mpfc is turned on and off at a high frequency and the voltage on cbus charges up to a specified voltage. the feedback loop of the irs2548d regulates this voltage to a fixed value by continuously monitoring the dc bus voltage and adjusting the on-time of mpfc accordingly. for an increasing dc bus the on-time is decreased and for a decreasing dc bus the on-time is increased. this negative feedback control is performed with a slow loop speed such that the average inductor current smoothly follows the low-frequency line input voltage for high power factor and low thd. the on-time of mpfc therefore appears to be fixed (except for on time modulation which is discussed later) over several cycles of the line voltage. with a fixed on- time and an off-time determined by the inductor current discharging to zero the switching frequency and duty cycle vary to produce a high frequency near the zero crossing of the ac input line voltage and a lower frequency at the peak (figure 5). v, i t figure 5: sinusoidal line input voltage (solid line), triangular pfc inductor current and smoothed sinusoidal line input current (dashed line) over one half-cycle of the ac line input voltage. when the line input voltage is low (near the zero crossing), the inductor current will charge to a lower peak level and therefore the discharge time will be fast resulting in a high switching frequency. when the input line voltage is high (near the peak), the inductor current will charge up to a higher amount and the discharge time will be longer giving a lower switching frequency. the pfc control circuit of the irs2548d (figure 6) includes five control pins: vbus, comp, zx, pfc and oc. the vbus pin measures the dc bus voltage via an external resistor voltage divider. the comp pin voltage at the transconductance error amplifier output sets the on-time of mpfc where the speed of the feedback loop is determined by the external comp capacitor. the zx input detects when the inductor current has discharged to zero each switching cycle using a secondary winding from the pfc inductor. the pfc output provides the gate driver output for the external mosfet, mpfc. the oc pin senses the current flowing through mpfc and performs cycle- by-cycle over-current protection.
irs2548d www.irf.com ? 2011 international rectifie r 16 rvbus1 rvbus2 rvbus ccomp lpfc mpfc rpfc dfpc cbus (+) (-) rzx pfc control vbus comp pfc zx com oc roc figure 6: irs2548d simplified pfc control circuit. the vbus pin is regulated against a fixed internal 4v reference voltage for regulating the dc bus voltage (figure 7). the feedback loop is performed by an operational transconductance amplifier (ota) that sinks or sources a current to the external capacitor at the comp pin. the resulting voltage on the comp pin sets the threshold for the charging of the internal timing capacitor and therefore determines the on-time of mpfc. 4 3 1 q s rq 2.0v vbus comp zx 5.1v 4.0v ota1 4.3v 5 pfc q s r 2 q r 1 comp3 comp4 comp5 rs 3 rs 4 vcc fault mode signal m1 watch dog timer m2 c1 3.0v discharge vcc to uvlo- comp2 6 oc 1.2v figure 7: irs2548d detailed pfc control circuit. the off-time of mpfc is determined by the time it takes the lpfc current to fall to zero. a positive- going edge at the zx input exceeding the internal 2v threshold (vzxth+) signals the beginning of the off-time and the following negative-going edge falling below 1.7v (vzxth+ - vzxhys) occurs when the lpfc current discharges to zero which signals the end of the off-time and mpfc is turned on again (figure 8). the cycle repeats itself indefinitely until the pfc section is disabled due to a fault detected by the system section (fault mode), an over-voltage on the dc bus or the negative transition of zx pin voltage does not occur. should the negat ive edge at zx not be detected, mpfc will remain off until the watch-dog timer forces it to turn-on again after a fixed delay. should the oc pin exc eed the 1.2v (vocth+) over-current threshold during the on-time, the pfc output will turn off. the circuit will then wait for a negative-going transition on the zx pin or a forced turn-on from the watch-dog timer to turn the pfc output on again. i lpfc pfc zx oc 1.2v . . . . . . . . . . . . figure 8: inductor current, pfc pin, zx pin and oc pin timing diagram. on-time modulation circuit a fixed on-time of mpfc ov er an entire cycle of the line input voltage produces a peak inductor current which naturally follows the sinusoidal shape of the line input voltage. the smoothed averaged line input current is in phase with the line input voltage for high power factor but some harmonic distortion is left. this is mostly due to cross-over distortion of the line current near the zero-crossings of the line input voltage. to achiev e lower harmonics that comply with international standards such as en61000-3-2 class c and general market requirements an additional on-time modulation circuit in included in the pfc control. this circuit dynamically increases the on-time of mpfc as the line input voltage nears the zero-crossings (figure 9). this causes the peak lpfc current and therefore the smoothed line input current to increase slightly near the zero-crossings of the line input voltage to compensate for cross over distortion which reduces the thd and higher harmonics.
irs2548d www.irf.com ? 2011 international rectifie r 17 0 0 i lpfc pfc pin near peak region of rectified ac line near zero-crossing region of rectified ac line figure 9: on-time modulation ci rcuit timing diagram dc bus over-voltage protection should over-voltage occu r on the dc bus and the vbus pin exceeds the internal 4.3v threshold (vbusov+), the pfc output is disabled (set to a logic ?low?). when the dc bus decreases again and the vbus pin decreases below the internal 4.15v threshold (vbusov-), a watch-dog pulse is forced on the pfc pin and normal pfc operation is resumed. iii. design equations (half-bridge) note: the results from the following design equations can differ slightly from actual measurements due to ic tolerances, component tolerances, and oscillator over- and under-shoot due to internal comparator response time. step 1: program run frequency the run frequency is programmed with the timing resistor rfmin at the fmin pin. the graph in figure 10 (rfmin vs. frequency) can be used to select rfmin value for desired run frequency. 20 40 60 80 100 120 140 160 180 10 15 20 25 30 35 40 45 50 equivalent rfmin (kohms) frequency (khz ) figure 10: graph of frequency against rfmin step 2: program maximum current the maximum current is programmed with the external resistor rcs and an internal threshold of 1.25v (vcsth+). this threshold determines the over-current limit of the system: cs max r i 25 . 1 = [amps peak] or max cs i r 25 . 1 = [ohms]
irs2548d www.irf.com ? 2011 international rectifie r 18 iv. pfc design equations step1: calculate pfc inductor value: vbus p f vac vac vbus l out min min min pfc ? ? ? ? ? ? ? = 2 ) 2 ( 2 [henries] where, vbus = dc bus voltage min vac = minimum rms ac input voltage = pfc efficiency (typically 0.95) min f = minimum pfc switching frequency at minimum ac input voltage out p = system output power step 2: calculate peak pfc inductor current: ? ? ? = min out pk vac p i 2 2 [amps peak] note: the pfc inductor must not saturate at pk i over the specified syst em operating temperature range. proper core sizing and air-gapping shoul d be considered in the inductor design. step 3: calculate pfc over-current resistor roc value: pk oc i r 25 . 1 = where vcsth+ = 1.25v [ohms]
irs2548d www.irf.com ? 2011 international rectifie r 19 package details
irs2548d www.irf.com ? 2011 international rectifie r 20 tape and reel details
irs2548d www.irf.com ? 2011 international rectifie r 21 part marking information
irs2548d www.irf.com ? 2011 international rectifie r 22 ordering information standard pack base part number package type form quantity complete part number tube/bulk 55 IRS2548DSPBF irs2548d soic14n tape and reel 2500 irs2548dstrpbf the information provided in this document is believed to be accu rate and reliable. however, international rectifier assumes no responsibility for the consequences of the use of this information. international rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result fr om the use of this information. no license is granted by imp lication or otherwise under any patent or patent rights of international rectif ier. the specifications ment ioned in this document are subj ect to change without notice. this document supersedes and replaces all inform ation previously supplied. for technical support, please contact ir?s technical assistance center http://www.irf.com/technical-info/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105

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